电子/通讯类 2021_09_06 每日一练
用FSM实现101101的序列检测模块。(南山之桥)
a为输入端,b为输出端,如果a连续输入为1101则b输出为1,否则为0。例如a: 00011001
10110100100110
b: 0000000000100100000000
请画出state machine;请用RTL描述其state machine。(未知)
To design a CMOS invertor with balance rise and fall time,please define the ration of channel width of PMOS and NMOS and explain?